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Tripath Technology, Inc. - Technical Information
TAA2009 STEREO 9W (8) CLASS-TTM DIGITAL AUDIO AMPLIFIER USING DIGITAL POWER PROCESSINGTM TECHNOLOGY
TECHNICAL INFORMATION Revision 1.02 - May 2006
GENERAL DESCRIPTION
The TAA2009 is a 9W/ch continuous average two-channel Class-T Digital Audio Power Amplifier IC using Tripath's proprietary Digital Power ProcessingTM technology. The TAA2009, in a QFN package, along with extremely high efficiency, allows for a very compact amplifier design. Class-T amplifiers offer both the audio fidelity of Class-AB and the power efficiency of Class-D amplifiers.
APPLICATIONS FEATURES
LCD TV's LCD Monitors Plasma TV's Computer/PC Multimedia Battery Powered Systems
BENEFITS
Fully integrated solution with FETs Compact packaging and board design Reduced system cost with no heat sink Differential inputs minimize common-mode noise Dramatically improves efficiency versus ClassAB Signal fidelity equal to high quality linear amplifiers High dynamic range compatible with digital media such as CD, DVD, and Internet audio Capable of driving a wide range of load impedances Sophisticated pop reduction circuit
TYPICAL PERFORMANCE
THD+N versus Output Power
10 VDD = 12V 5 2
f = 1kHz Gain1=0, Gain0=1 BW = 22Hz - 20kHz(AES17)
Class-T architecture Single Supply Operation "Audiophile" Quality Sound 0.05% THD+N @ 5W, 8 0.16% IHF-IM @ 1W, 8 6.4W @ 8, 0.1% THD+N 3.5W @ 16, 0.1% THD+N High Power 10.6W @ 6, 10% THD+N 9W @ 8, 10% THD+N 5W @ 16, 10% THD+N Extremely High Efficiency 90% @ 5W, 16 86% @ 9W, 8 Dynamic Range = 96 dB Mute and Sleep modes Improved turn-on & turn-off pop suppression Over-current protection with automatic restart circuit Over-temperature protection Space saving 32-pin 8mm x 8mm x 1mm QFN package with exposed pad Filterless Operation Option
32-pin QFN (Top View)
IN2M C2 INL V5A BIASCAP AGND C1 IN1M
THD+N (%)
1 0.5 0.2 0.1 0.05
RL = 16 R L = 8 RL = 4 RL = 6
IN1P V5D GAIN0 DGND REF SLEEP MUTE FAULT 1 2 3 4 5 6 7 8
26 27 28 29 30 31 32 11 10 9 VDD2 PGND2 OUTM2 OUTM1 PGND1 VDD1 OUTP1
25 OUTP2
24 23 22 21 20 19 18 17
IN2P AGND GAIN1 5VGEN VDDA DCAP CPUMP SUB
16 15 14 13 12
0.02 0.01 1 2 3 4 5 6 7 8 9 10 20
Output Power (W)
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A B S O L U T E M A X I M U M R A T I N G S (Note 1)
SYMBOL VDD MUTE, SLEEP, GAIN1, GAIN0, INL TSTORE TA ESDHB MUTE Input Voltage Storage Temperature Range Operating Free-air Temperature Range ESD Susceptibility - Human Body Model (Note 2) PARAMETER Supply Voltage (note 1) Value 14 -0.3 to V5 + 0.3 -40 to 150 -40 to +85 1500 UNITS V V C C V
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Please note that this is not a valid "operating condition". The maximum voltage on the VDD pins during operation is 13.2V. Refer to the Maximum Supply Voltage section on page 13. Note 2: Human body model, 100pF discharged through a 1.5K resistor.
OPERATING CONDITIONS -40oC to +85OC
SYMBOL VDD VIH VIL Supply Voltage (note 1)
(Note 3)
PARAMETER High-level Input Voltage (MUTE, SLEEP, GAIN1, GAIN0, INL) Low-level Input Voltage (MUTE, SLEEP, GAIN1, GAIN0, INL)
MIN. 8.5 4.2
TYP. 12
MAX. 13.2 1.0
UNITS V V V
Note 3: Recommended Operating Conditions indicate conditions for which the device is functional. See Electrical Characteristics for guaranteed specific performance limits.
THERMAL CHARACTERISTICS
SYMBOL JA PARAMETER Junction-to-ambient Thermal Resistance (note 4) VALUE 21 UNITS C/W
Note 4: The JA value is based on the exposed pad being soldered down to the printed circuit board. The exposed pad must be soldered to an exposed copper area on the printed circuit board for proper thermal and electrical performance. The exposed pad is at substrate ground.
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E L E C T R I C A L C H A R A C T E R I S T I C S (Note 5)
See Application/Test Circuit with single ended inputs and filtered outputs. Unless otherwise specified, VDD = 12V, f = 1kHz, Gain1=0, Gain0=1 Measurement Bandwidth = 20kHz, RL = 8, TA = 25 C, package exposed pad soldered to the printed circuit board.
SYMBOL PO PARAMETER Output Power (Continuous Average/Channel) CONDITIONS THD+N = 0.1% RL = 6 RL = 8 RL = 16 RL = 6 RL = 8 RL = 16 MIN. TYP. 7.8 6.4 3.5 10.6 9 5 28 7 60 0.05 0.16 96 96 70 85 86 -10 50 4.5 0.5 160 10 MAX. UNITS W W W W W W mA mA mA % % dB dB dB dB % mV mV V V V
THD+N = 10%
IDD,MUTE IDD, SLEEP Iq THD + N IHF-IM SNR CS PSRR VOFFSET1 VOFFSET2 VOH VOL eOUT
Mute Supply Current Sleep Supply Current Quiescent Current Total Harmonic Distortion Plus Noise IHF Intermodulation Distortion Signal-to-Noise Ratio Channel Separation Power Supply Rejection Ratio Power Efficiency
MUTE = VIH SLEEP = VIH VIN = 0 V PO = 5W/Channel 19kHz, 20kHz, 1:1 (IHF), Po = 1W A-Weighted, POUT = 9W, RL = 8 f = 1 kHz 20 Hz < f < 20 kHz VDD = 9V to 13.2V POUT = 9W/Channel, RL = 8
Dynamic Output Offset MUTE transition from high to low Voltage (note 6) Static Output Offset Voltage MUTE = low High-level output voltage (FAULT) Low-level output voltage (FAULT) Output Noise Voltage -40C to +85C, IOH = 250uA -40C to +85C, IOL= 250uA A-Weighted, input AC grounded
Note 5: Minimum and maximum limits are guaranteed but may not be 100% tested. Note 6: Refer to the Dynamic DC Offset Calibration section on page 14 for a detailed description of Dynamic Offset Voltage.
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TAA2009 PINOUT
32-pin QFN (Top View)
BIASCAP AGND C1 IN1M 29 30 31 32 1 2 3 4 5 6 7 8 13 12 11 10 9 IN2M C2 INL V5A 26 27 28 25 24 23 22 21 20 19 18 17 16 15 14 IN2P AGND GAIN1 5VGEN VDDA DCAP CPUMP SUB
IN1P V5D GAIN0 DGND REF SLEEP MUTE FAULT
VDD2 PGND2 OUTM2 OUTM1 PGND1 VDD1 OUTP1
OUTP2
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PIN DESCRIPTION
Pin 1, 24 2, 28 3, 22 Function IN1P, IN2P V5D, V5A GAIN0, GAIN1 Description Positive audio input for channel 1 and channel 2 Digital 5VDC, Analog 5VDC Gain select bits. GAIN0 is least significant bit. See Applications Information for programmable gain values. Both GAIN 0 and GAIN1 have internal 50K pulldown resistors. Digital Ground. Connect to AGND locally (near the TAA2009). Internal reference voltage; approximately 1.0 VDC. When set to logic high, device goes into low power mode. If not used, this pin should be grounded When set to logic high, both amplifiers are muted and in idle mode. When low (grounded), both amplifiers are fully operational. If left floating, the device stays in the mute mode. This pin should be tied to GND if not used. A logic high output indicates an under-voltage condition, thermal overload, and an output is shorted to ground, or another output. Bridged output pairs Supply pins for high current H-bridges, nominally 12VDC. Power Grounds (high current) Substrate connection. Connect to PGND. Charge pump input (nominally 10V above VDDA) Charge pump switching output pin. DCAP is a free running 350kHz square wave between VDDA and DGND (12Vpp nominal). Power supply for analog VDD circuitry. Connect to same supply as VDD1 and VDD2. Regulated 5VDC source used to supply power to the input section (pins 2 and 28). Analog Ground. Connect all pins together directly at the TAA2009. Negative audio input for channel 2 and channel 1. Pop minimization capacitor. Use 10uF. Modulation selection pin. Connecting the INL pin to a logic high level enables the inductor-less mode. This mode allows the TAA2009 to be operated without an output filter as the switching outputs are in phase with zero input. If INL is tied to a logic low or left floating (pulled down via internal 50K resistor to ground), the INL mode will be disabled. This results in a differential output switching pattern typical of previous Tripath generation parts such as TA2024 and TAA2008. The state of the INL pin should only be changed with MUTE at a logic high state. Input stage bias voltage (approximately 2.4VDC).
4 5 6 7 8 9, 12 16, 13 10, 15 11, 14 17 18 19 20 21 23, 30 25, 32 26, 31 27
DGND REF SLEEP MUTE FAULT OUTP1 & OUTM1 OUTP2 & OUTM2 VDD1, VDD2 PGND1, PGND2 SUB CPUMP DCAP VDDA 5VGEN AGND, AGND IN2M, IN1M C2, C1 INL
29
BIASCAP
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APPLICATION / TEST CIRCUIT WITH DIFFERENTIAL INPUTS AND FILTERED OUTPUTS
TAA2009
CI 1.0uF DIFFERENTIAL AUDIO INPUT CP 10uF (Pin 30) CA 1.0uF (Pin 30) 5V
MUTE 7
VDD1
IN1P 1
9 OUTP1
+ -
Lo 10uH, 2A
IN1M 32
CI 1.0uF
C1 31
Processing & Modulation
GAIN CONTROL
PGND1 VDD1
(Pin 11) Lo 10uH, 2A
Co 0.22uF
CZ 0.22uF CDO 0.01uF RL 6 to16
GAIN0
3 GAIN1 22
12 OUTM1
Co 0.22uF
RZ 10, 1/4W
BIASCAP 29
V5
PGND1
8
VDD2
CP 10uF (Pin 27) DIFFERENTIAL AUDIO INPUT CI 1.0uF
FAULT
C2 26 IN2P 24
16 OUTP2
+ -
Lo 10uH, 2A
IN2M 25
CI 1.0uF (Pin 4) RREF 20.0K, 1%
5
REF
Processing & Modulation
PGND2 VDD2
(Pin 14) Lo 10uH, 2A
Co 0.22uF
CZ 0.22uF CDO 0.01uF
13 OUTM2 18 CPUMP 19 DCAP
Co RZ 0.22uF 10, 1/4W
RL 6 to 16
DCP CCP 1uF
To pin 20 (VDDA)
PGND2
CPUMP VDDA
CD 0.1uF DCP
18
+
VDD 1M
20 23 21
CP 1uF CS 0.1uF CS 0.1uF To Pins 2, 28
27 INL 6
SLEEP V5D DGND V5 A AGND
AGND 5VGEN
N.C.
2
CS 1.0uF
4 28
VDD1
10
CSW 0.1uF
+
VDD CSW
To Pin 21
CS 1.0uF
PGND1 11
100uF, 16V
30
VDD2
15 14
CSW 0.1uF
+
17
SUB
CSW
PGND2
100uF, 16V
Note: Analog and Digital/Power Grounds must be connected locally at the TAA2009 Analog Ground Power Ground
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APPLICATION / TEST CIRCUIT WITH SINGLE ENDED INPUTS AND FILTERED OUTPUTS
TAA2009
CI 1.0uF SINGLE ENDED AUDIO INPUT CP 10uF (Pin 30) CA 1.0uF (Pin 30) 5V
MUTE 7
VDD1
IN1P 1
9 OUTP1
+ -
Lo 10uH, 2A
IN1M 32
RI
CI 1.0uF
C1 31
Processing & Modulation
GAIN CONTROL
PGND1 VDD1
(Pin 11)
Co 0.22uF
CZ 0.22uF CDO 0.01uF RL 6 to 16
GAIN0
3 GAIN1 22
Lo 12 OUTM1 10uH, 2A
Co 0.22uF
RZ 10, 1/4W
BIASCAP 29
V5
PGND1
8
VDD2
CP 10uF (Pin 27) CI 1.0uF
FAULT
C2 26 IN2P 24
16 OUTP2
+ -
Lo 10uH, 2A
SINGLE ENDED AUDIO INPUT RI (Pin 4)
IN2M 25
CI 1.0uF
5
RREF 20.0K, 1%
REF
Processing & Modulation
PGND2 VDD2
(Pin 14) Lo 10uH, 2A
Co 0.22uF
CZ 0.22uF CDO 0.01uF RL 6 to 16
13 OUTM2 18 19
Co RZ 0.22uF 10, 1/4W
DCP CCP 1uF
To pin 20 (VDDA)
CPUMP DCAP
PGND2
CPUMP VDDA
CD 0.1uF DCP
18
+
VDD 1M
20 23 21
CP 1uF CS 0.1uF CS 0.1uF To Pins 2, 28
27 INL 6
SLEEP V5D DGND V5 A AGND
AGND 5VGEN
N.C.
2
CS 1.0uF
4 28
VDD1
10
CSW 0.1uF
+
VDD CSW
To Pin 21
CS 1.0uF
PGND1 11
100uF, 16V
30
VDD2
15 14
CSW 0.1uF
+
17
SUB
CSW
PGND2
100uF, 16V
Note: Analog and Digital/Power Grounds must be connected locally at the TAA2009 Analog Ground Power Ground
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APPLICATION / TEST CIRCUIT WITH DIFFERENTIAL INPUTS AND FILTERLESS OUTPUTS
TAA2009
CI 1.0uF DIFFERENTIAL AUDIO INPUT CP 10uF (Pin 30) CA 1.0uF (Pin 30) 5V
MUTE 7
VDD1
IN1P 1
9 OUTP1
+ -
IN1M 32
CI 1.0uF
C1 31
Processing & Modulation
GAIN CONTROL
PGND1 VDD1 RL 6 to16
GAIN0 3 GAIN1 22 BIASCAP 29
12 OUTM1
V5
PGND1
8
VDD2
CP 10uF (Pin 27) DIFFERENTIAL AUDIO INPUT CI 1.0uF
FAULT
C2 26 IN2P 24
16 OUTP2
+ -
IN1M 25
CI 1.0uF (Pin 4) RREF 20.0K, 1%
5
REF
Processing & Modulation
PGND2 VDD2 RL 6 to 16
13 OUTM2 18 CPUMP 19 DCAP
DCP CCP 1uF
To pin 20 (VDDA)
PGND2
CPUMP VDDA
CD 0.1uF DCP To Pin 21
18
+
VDD 1M
20 23 21
CP 1uF CS 0.1uF CS 0.1uF To Pins 2, 28
27 INL
AGND
6
N.C.
SLEEP
5VGEN
2
CS 1.0uF
V5D DGND V5A AGND VDD2 VDD1 PGND1
4 28
10 11
CSW 0.1uF
+
VDD CSW
To Pin 21
CS 1.0uF
100uF, 16V
30
15
CSW 0.1uF
+
17
SUB
14 PGND2
CSW
100uF, 16V
Note: Analog and Digital/Power Grounds must be connected locally at the TAA2009 Analog Ground Power Ground
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APPLICATION / TEST CIRCUIT WITH SINGLE ENDED INPUTS AND FILTERLESS OUTPUTS
TAA2009
CI 1.0uF SINGLE ENDED AUDIO INPUT CP 10uF (Pin 30) CA 1.0uF (Pin 30) 5V
MUTE 7
VDD1
IN1P 1
9 OUTP1
+ -
IN1M 32
RI
CI 1.0uF
C1 31
Processing & Modulation
GAIN CONTROL
PGND1 VDD1 RL 6 to 16
GAIN0 3 GAIN1 22 BIASCAP 29
12 OUTM1
V5
PGND1
8
VDD2
CP 10uF (Pin 27) SINGLE ENDED AUDIO INPUT RI (Pin 4) CI 1.0uF
FAULT
C2 26 IN2P 24
16 OUTP2
+ -
IN2M 25
CI 1.0uF
5
RREF 20.0K, 1%
REF
Processing & Modulation
PGND2 VDD2 RL 6 to 16
13 OUTM2 18 CPUMP 19 DCAP
DCP CCP 1uF
To pin 20 (VDDA)
PGND2
CPUMP VDDA
CD 0.1uF DCP To Pin 21
18
+
VDD 1M
20 23 21
CP 1uF CS 0.1uF CS 0.1uF To Pins 2, 28
27 INL 6
SLEEP V5D DGND V5A AGND
AGND 5VGEN
N.C.
2
CS 1.0uF
4 28
VDD1 PGND1
10 11
CSW 0.1uF
+
VDD CSW
To Pin 21
CS 1.0uF
100uF, 16V
30
VDD2
15
CSW 0.1uF
+
17
SUB
14 PGND2
CSW
100uF, 16V
Note: Analog and Digital/Power Grounds must be connected locally at the TAA2009 Analog Ground Power Ground
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External Components Description (REFER TO THE APPLICATION/TEST
CIRCUIT)
Components CI RI CP RREF CA CD DCP CCP
Description AC input coupling capacitor which, in conjunction with RI, forms a highpass filter at
fC = 1 (2RICI )
CS CSW
CZ RZ
LO
Input resistor. Used only in applications where the audio source has a single ended output. The resistor value should match the audio source's output impedance. Capacitor used to eliminate turn-on and turn-off pops. One capacitor is used for each channel. Please use 10uF for this capacitor. This resistor should be grounded at the same channels CSW ground connection. Bias resistor. Locate close to pin 25 (REF) and ground at pin 24 (AGND1). BIASCAP decoupling capacitor. Locate close to pin 3 (BASCAP) and ground at pin 4 (AGND3). Charge pump input capacitor. This capacitor should be connected directly between pins 19 (DCAP) and the external diodes (DCP) and located physically close to the TAA2009. External diodes used to create charge pump power supply. Please refer to the Application / Test Circuit for proper connection Charge pump output capacitor that enables efficient high side gate drive for the internal H-bridges. To maximize performance, this capacitor should be connected directly between pin 18 (CPUMP) and pin 17 (VDDA). Please observe the polarity shown in the Application / Test Circuit. Supply decoupling for the low current power supply pins. For optimum performance, these components should be located close to the pin and returned to their respective ground as shown in the Application/Test Circuit. Supply decoupling for the high current, high frequency H-Bridge supply pins. These components must be located as close to the device as possible to minimize supply overshoot and maximize device reliability. Both the high frequency bypassing (0.1uF) and bulk capacitor (100uF/220uF) should have good high frequency performance including low ESR and low ESL. Recommended capacitor families include Nichicon HE series and Panasonic FM series for thru-hole types. Qualified SMT electrolytics include Nichicon UD series and Panasonic FK series. Zobel Capacitor. Zobel resistor, which in conjunction with CZ, terminates the output filter at high frequencies. The combination of RZ and CZ minimizes peaking of the output filter under both no load conditions or with real world loads, including loudspeakers which usually exhibit a rising impedance with frequency. Output inductor, which in conjunction with CO and CDO, demodulates (filters) the switching waveform into an audio signal. Forms a second order filter with a cutoff frequency of f C = 1 ( 2 L O C TOT ) and a quality factor of
Q = R L C TOT
CO CDO
2 L O C TOT where CTOT = CO || 2 * CDO.
Output capacitor. Differential Output Capacitor. Differential noise decoupling for reduction of conducted emissions. Must be located near chassis exit point for maximum effectiveness.
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TYPICAL PERFORMANCE WITH SINGLE ENDED INPUTS AND FILTERED OUTPUTS
THD+N versus Output Power
10 VDD = 12V 5 2
f = 1kHz Gain1=0, Gain0=1 BW = 22Hz - 20kHz(AES17)
Efficiency versus Output Power
100 90 80 70
THD+N (%)
1 0.5 0.2 0.1 0.05 0.02 0.01 1 2 3 4 5 6 7 8 9 10 20
RL = 16 R L = 8 R L = 4 R L = 6
Eff(%)
60 50 40 30 20 10 0 0 1 2 3 4 5 6
VDD = 12V RL= 8 f= 1kHz BW = 22Hz - 20kHz(AES17)
7
8
9
10
Output Power (W)
Output Pow er (Per Channel) - W
Intermodulation Distortion
+0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 20 50 100 200 500 1k 2k 5k 10k 20k 30k
19kHz, 20kHz, 1:1 VDD = 12V Po = 1W RL = 8 32k FFT FS = 65kHz BW = 22Hz - 80kHz
100 90 80 70
Efficiency versus Output Power
FFT (dBr)
Eff(%)
60 50 40 30 20 10 0 0 1 2 3 4
VDD = 12V RL = 6 f= 1kHz BW = 22Hz - 20kHz(AES17)
Frequency (Hz)
6 8 5 7 9 Output Pow er (Per Channel) - W
10
11
12
THD+N versus Frequency
1 .5 Po = 1W .2
VDD = 12V RL = 8 BW = 22Hz - 22kHz
Channel Separation versus Frequency
+0 -10
VDD = 12V Po = 1W RL = 8 BW = 22Hz - 22kHz
Channel Separation (dBr)
-20 -30 -40 -50 -60 -70 -80 -90 -100 -110 20
THD+N (%)
.1 0.05 0.02 0.01 0.005 0.002 0.001 20 50 100 200 500 1k 2k 5k 10k 20k
50
100
200
500
1k
2k
5k
10k
20k
Frequency (Hz)
Frequency (Hz)
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TYPICAL PERFORMANCE WITH SINGLE ENDED INPUTS AND FILTERED OUTPUTS
Frequency Response
+3 +2.5 VDD = 12V +2
Pout = 1W Gain1=0, Gain0=1 RL = 16 RL = 8
Power Dissipation versus Total output Power
3 2
Output Amplitude (dBr)
+1.5 +1 +0.5 +0 -0.5 -1 -1.5 -2 -2.5 -3 20 50 100 200 500 1k 2k 5k
2.5
Pdiss (W)
1.5
RL = 6
1
VDD = 12V RL = 8 f= 1kHz BW = 22Hz - 20kHz(AES17)
.5
0
10k
20k
0
2
4
6
8
10
12
14
16
18
20
Frequency (Hz)
Total Output Pow er (W)
Power Dissipation versus Total output Power
5
4
Pdiss (W)
3
2
1
VDD = 12V RL = 6 f= 1kHz BW = 22Hz - 20kHz(AES17)
0
0
1
2
3
4
5
6
7
8
9
10
11
12
Total Output Pow er (W)
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APPLICATION INFORMATION Layout Recommendations
The TAA2009 is a power (high current) amplifier that operates at relatively high switching frequencies. The outputs of the amplifier switch between the supply voltage and ground, at high speeds, while driving high currents. This high-frequency digital signal is passed through an LC low-pass filter to recover the amplified audio signal. Since the amplifier must drive the inductive LC output filter and speaker loads, the amplifier outputs can be pulled above the supply voltage and below ground by the energy in the output inductance. To avoid subjecting the TAA2009 to potentially damaging voltage stress, it is critical to have a good printed circuit board layout. It is recommended that Tripath's layout and application circuit be used for all applications and only be deviated from after careful analysis of the effects of any changes. Please contact Tripath Technology for further information regarding reference design material regarding the TAA2009.
Maximum Supply Voltage
The absolute maximum allowable voltage on the VDD supply pins (pins 10, 15, and 20) is 14V. Device damage can occur above this voltage. Please note that this is not a valid "operating condition". The maximum voltage on the VDD pins during operation is 13.2V. During normal operation, the output pins (pins 9, 12, 13, and 16) may experience overshoot voltages due to inductive kickback that are above 14V. These pins can tolerate overshoot of up to 18V. However, care should be taken to properly decouple the VDD pins. Overshoot on the output pins can travel through the TAA2009 output devices and appear on the VDD pins. Without proper power supply decoupling, this can cause ripple voltages on the VDD pins that might exceed their absolute maximum voltage. However, this will only happen in extreme cases and can be prevented by placing the high frequency decoupling capacitors close to the VDD pins.
TAA2009 Input Stage
The input stage of the TAA2009 is configured as a differential receiver to maximize common mode rejection in typical audio circuits. To maximize this benefit, the INxP and INxM should be driven with out of phase signals from sources that have the same output impedance. Also, the signal from the sources should be routed in a parallel fashion from the source. In some instances, there will be a necessity to drive the TAA2009 with a single-ended input signal. In this case, the unused input should be AC coupled to Power Ground using the same value of CI implemented for the driven channel. Either input, INxP or INxM, can be used for the signal input. To minimize the effects of ground noise in the system, CI should be terminated at the CSW ground connection point through a resistor. Please refer to Figure 1. The value of the resistor should match the output impedance of the audio source. Please refer to the Applications Schematic for component locations and descriptions.
AUDIOSOURCE T AA2009
IN1P Zout CI IN1M Zout = RI RI CI
Figure 1
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Dynamic DC offset Calibration
One of the major causes of turn-on and turn-off pop is DC offset. Typically, when a system turns on (begins switching), the potential across the speaker changes abruptly from 0V to whatever the DC offset voltage of the system is. Similarly, when the system turns off, the potential changes abruptly from the DC offset voltage to 0V. This abrupt change is heard as a pop. The TAA2009 employs a patent pending method for reducing pop. At the start of switching, a calibration circuit minimizes the potential across the speaker to the "dynamic DC offset" voltage. Then, the potential is ramped up (or down) to the "static DC offset" voltage where it remains during normal operation. (See Figure 2 and Figure 3) This ramp is slow enough to keep the speaker movement in the subsonic range. During turn-off, this procedure is reversed. The static DC offset voltage is ramped down to the static DC offset level before switching stops. Dynamic offset cancellation requires equal impedances on the positive and negative inputs. If a single ended audio source with a 600 output impedance is connected to IN1P (through a DC blocking capacitor), then IN1M must be terminated to ground with a 600 resistor (also through a DC blocking capacitor). Please refer to figure 1.
Unmute Output Voltage (V)
see expanded below
Static offset Voltage
Time
Figure 2
Unmute 0V Output Voltage (V) Dynamic Offset Voltage Time
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Figure 3 TAA2009 Amplifier Gain
The closed loop gain of the TAA2009 is externally configurable via two input pins, GAIN0 and GAIN1. The table below shows the three different gain values available based on the pin voltages at GAIN0 and GAIN1. Internally, different input resistor values are used to implement the three gain settings. Thus, the input impedance will change based on gain setting. The gain tracking is very tightly matched from device to device, but the absolute input impedance will vary +/-25% due to process variations. This variation must be considered when choosing the proper value of Ci (see discussion below).
TAA2009 AMPLIFIER GAIN SETTING GAIN1 0 1 1 GAINO 1 0 1 GAIN (V/V) 12 20 30 GAIN (dB) 21.6 26 29.5 INPUT IMPEDANCE (k) 33.95 20.4 13.6
The low frequency roll-off characteristic is dictated by the choice of CI and RI. As noted previously, the input impedance varies depending on gain setting. Based on a +/-25% variation of input resistance, the minimum input resistance is 10.2k (for 30V/V gain setting) and the maximum input resistance is 84.9k (for the 6V/V gain setting) The -3dB frequency is:
f
- 3dB
=
1 2 C I R I
On the EB-TAA2009, a value of 1.0F is used for CI which creates a nearly flat response down to 20Hz even for the 30V/V gain setting. In many cases, a lower value of CI can be used due to a lower gain setting, or because the speakers used in LCD TV's or similar applications do not have the ability to reproduce low frequency signals.
Mute Pin
The mute pin must be driven to a logic low or logic high state for proper operation. To enable the amplifier, connect the mute pin to a logic low. To enable the mute function, connect the mute pin to a logic high signal. Please note that the mute pin is a 5V CMOS input pin and the mute signal should be de-bounced to eliminate a possibility of falsely muting. When in mute, the internal processor bias voltages are still active in the TAA2009. This minimizes any turn on pop caused by charging the input coupling capacitor. It is recommended that the mute pin is held high during power up or power down to eliminate audible transients. If turn-on and/or turn-off noise is still present with a TAA2009 amplifier, the cause may be other circuitry external to the TAA2009 such as an audio processor or preamp. Multiple audio processors used in LCD TV's create audible pops as their power supply collapses. If the TAA2009 is still active (mute pin is low), then these audible pops will be amplified and output to the speakers. To eliminate this problem, simply activate the mute before the power supply collapses.
Sleep Pin
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The SLEEP pin is a 5V logic input that when pulled high puts the part into a low quiescent current mode. To disable SLEEP mode, the sleep pin should be grounded.
INL Pin
The INL pin selects the modulation scheme mode. Connecting the INL pin to a logic high level enables the inductor-less mode. This mode allows the TAA2009 to be operated without an output filter as the switching outputs are in phase with zero input. If INL is tied to a logic low or left floating (pulled down via the internal 50K resistor to ground), the INL mode will be disabled. This results in a differential output switching pattern typical of previous Tripath generation parts such as TA2024 and TAA2008. The state of the INL pin should only be changed with MUTE at a logic high state.
Protection Circuits
The TAA2009 is guarded against over-temperature and over-current conditions. When the device goes into an over-temperature or over-current state, the FAULT pin goes to a logic HIGH state indicating a fault condition. When this occurs, the amplifier is muted, all outputs are TRISTATED, and will float to 1/2 of VDD. The amplifier will automatically attempt to recover from a fault condition every 1 second and will enter fault again, if the cause for the original fault is still present (such as a speaker output still being shorted to ground).
Over-temperature Protection
An over-temperature fault occurs if the junction temperature of the part exceeds approximately 155C. The thermal hysteresis of the part is approximately 45C, therefore the fault will automatically clear when the junction temperature drops below 110C.
Over-current Protection
An over-current fault occurs if more than approximately 4 amps of current flows from any of the amplifier output pins. This can occur if the speaker wires are shorted together or if one side of the speaker is shorted to ground.
Fault Pin
The FAULT pin is a 5V logic output that indicates various fault conditions within the device. These conditions include: low supply voltage, low charge pump voltage, low 5V regulator voltage, over current at any output, and junction temperature greater than approximately 155C. All faults automatically reset upon removal of the condition.
Power Dissipation Derating
The TAA2009, as a result of high efficiency and good package thermal characteristics, can operate at elevated ambient temperatures without having to derate the output power, assuming 8 ohm output loads or higher. This in stark contrast to many other "competitive" solutions from other semiconductor vendors, many of which can only provide full power at ambient temperatures of 25C, or slightly higher, without exceeding a junction temperature of 150C. Lower die temperatures result in a more robust and reliable amplifier solution that can only be facilitated by a combination of high efficiency and good package thermal characteristics. The exposed pad must be soldered to the PC Board to increase the maximum power dissipation capability of the TAA2009 package. Soldering will minimize the likelihood of an overtemperature fault occurring during continuous heavy load conditions. There should be vias for connecting the exposed pad to the copper area on the printed circuit board.
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Conducting initial testing or characterization without the exposed pad soldered to the printed circuit board will give erroneous case temperature measurements. The TAA2009 is an extremely robust device; so not soldering the device to the printed circuit board, due to potential rework issues, should not be a concern. These devices do not fail unless the operating supply voltages maximums are exceeded, and/or an improper printed board design is utilized. The maximum device power dissipation, for a given ambient temperature, can be calculated based on a 150C maximum junction temperature, TJMAX, as given by the following equation:
PDISS = (TJMAX - TA ) JA
where: PDISS = maximum power dissipation TJMAX = maximum junction temperature of TAA2009 TA = operating ambient temperature JA = junction-to-ambient thermal resistance = 21C/W when soldered to PCB From the above formula, the maximum power dissipation at an ambient temperature of 25C is 5.95W, and at 85C is 3.10W.
Performance Measurements of the TAA2009
The TAA2009 operates by generating a high frequency switching signal based on the audio input. This signal is sent through a low-pass filter (external to the Tripath amplifier) that recovers an amplified version of the audio input. The frequency of the switching pattern is spread spectrum and typically varies between 100kHz and 1.0MHz, which is well above the 20Hz - 20kHz audio band. The pattern itself does not alter or distort the audio input signal but it does introduce some inaudible components. The measurements of certain performance parameters, particularly noise related specifications such as THD+N, are significantly affected by the design of the low-pass filter used on the output as well as the bandwidth setting of the measurement instrument used. Unless the filter has a very sharp roll-off just beyond the audio band or the bandwidth of the measurement instrument is limited, some of the inaudible noise components introduced by the Tripath amplifiers switching pattern will degrade the measurement. One feature of the TAA2009 is that it does not require large multi-pole filters to achieve excellent performance in listening tests, usually a more critical factor than performance measurements. Though using a multi-pole filter may remove high-frequency noise and improve THD+N type measurements (when they are made with wide-bandwidth measuring equipment), these same filters degrade frequency response. The TAA2009 Evaluation Board uses the Test/Application Circuit in this data sheet, which has a simple two-pole output filter and excellent performance in listening tests. Measurements in this data sheet were taken using this same circuit with a limited bandwidth setting in the measurement instrument.
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PACKAGE INFORMATION
32 PIN QFN - 8MM x 8MM X 1MM
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Tripath Technology Inc. reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Tripath does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. Tripath and Digital Power Processing are trademarks of Tripath Technology Inc. Other trademarks referenced in this document are owned by their respective companies. TRIPATH'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN CONSENT OF THE PRESIDENT OF TRIPATH TECHNOLOGY INC. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in this labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
Contact Information
TRIPATH TECHNOLOGY, INC 2560 Orchard Parkway, San Jose, CA 95131 408.750.3000 - P 408.750.3001 - F For more Sales Information, please visit us @ www.tripath.com/cont_s.htm For more Technical Information, please visit us @ www.tripath.com/data.htm
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